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W948D6FB / W948D2FB
256Mb Mobile LPDDR
(256Mb, X32)
PARAMETER
Operating one
bank active-
precharge
current
SYMBOL
IDD0
TEST CONDITION
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is
HIGH between valid commands; address inputs are
SWITCHING; data bus inputs are STABLE
-5
40
-6
38
- 75
35
UNIT
mA
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
IDD2P
IDD2PS
all banks idle, CKE is LOW; CS is HIGH,
tCK = tCKmin ; address and control inputs are
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK
= LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are
STABLE
Low
power
Normal
power
Low
power
Normal
power
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
mA
mA
Precharge non
all banks idle, CKE is HIGH; CS is HIGH, tCK =
power-down
standby current
Precharge non
power-down
standby current
IDD2N
IDD2NS
tCKmin; address and control inputs are SWITCHING;
data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
10
3
10
3
10
3
mA
mA
with clock stop
Active power-
SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, tCK =
down standby
current
Active power-
down standby
current with clock
IDD3P
IDD3PS
tCKmin; address and control inputs are SWITCHING;
data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
3
3
3
3
3
3
mA
mA
stop
Active non
SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK =
power-down
standby current
Active non
power-down
standby current
IDD3N
IDD3NS
tCKmin; address and control inputs are SWITCHING;
data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK =
LOW, CK = HIGH; address and control inputs are
25
15
20
12
20
12
mA
mA
with clock stop
SWITCHING; data bus inputs are STABLE
Operating burst
read current
Operating burst
write current
Auto-Refresh
Current
Deep Power-
Down current
IDD4R
IDD4W
IDD5
IDD8(4)
one bank active; BL = 4; CL = 3; tCK = tCKmin ;
continuous read bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; t CK = tCKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data
change each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
Address and control inputs are STABLE; data bus inputs
are STABLE
75
55
50
10
70
50
50
10
70
50
50
10
mA
mA
mA
uA
Notes:
1.
2.
3.
4.
IDD specifications are tested after the device is properly initialized.
Input slew rate is 1V/ns.
Definitions for IDD:
LOW is defined as V IN ≤ 0.1 * V DDQ ;HIGH is defined as V IN ≥ 0.9 * V DDQ ;STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
IDD8 is a typical value at 25 °C .
Publication Release Date : Oct, 15, 2012
- 49 -
Revision : A01-004
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